New IEEE VLSI Projects

Latest IEEE VLSI Projects Topics

Design and Implementation of 10/100 Mbps (Mega bits per second) Ethernet Switch for Network applications (2010)
Design and Implementation of USB 2.0 Transceiver Macro-cell Interface (UTMI) (2010)
A Versatile Multimedia Functional Unit Design Using the Spurious Power Suppression Technique (2010)
Design and Implementation of Digital low power base band processor for RFID Tags (2010)
Design and Implementation of Reversible Watermarking for JPEG2000 Standard
FPGA Implementation of 3D Discrete Wavelet Transform for Real-Time Medical Imaging
Design and Implementation of High Speed DDR SDRAM (Dual Data Rate Synchronously Dynamic RAM) Controller (2010)
Design and Implementation of Lossless DWT/IDWT for Medical Images
High Performance Complex Number Multiplier Using Booth-Wallace Algorithm
High Speed Parallel CRC Implementation Based On Unfolding, Pipelining and Retiming
Design of an Bus Bridge between OCP and AHB Protocol (2010)
Design of Gigabit Ethernet MAC (Medium Access Control) Transmitter
Design of an AMBA-Advanced High performance Bus (AHB) Protocol IP Block
Design of Data Encryption Standard (DES)
Design of Distributed Arithmetic FIR Filter

Design of Universal Asynchronous Receiver Transmitter (UART)
Design of Triple Data Encryption Standard (DES)
Design of 16 Point Radix-4 FFT (Fast Fourier Transform) Algorithm
Design of Dual Elevator Controller
Design of an ATM (Automated Teller Machine) Controller
Design of 8-Bit Pico Processor (VHDL)
Design of JPEG Image compression standard
Design of Digital FM Receiver using PLL (Phase Locked Loop)
Design of 16-bit QPSK (Quadrature Phase Shift Keying)
Design of 16-bit QAM (Quadrature Amplitude Modulation) Modulator
Design of AES (Advanced Encryption Standard) Encryption Algorithm with 128- bits Key Length
Design of RS-232 System Controller
Design of CRC (Cyclic Redundancy Check) Generator (Verilog)
Design and Implementation of OFDM Transmitter (VHDL)
Design of 8-bit Microcontroller (VHDL)
A New VLSI Architecture of Parallel Multiplier–Accumulator Based on Radix-2 Modified Booth Algorithm
An Efficient Architecture for 3-D Discrete Wavelet Transform
The Design of FIR Filter Base on Improved DA Algorithm and its FPGA Implementation

Design of On-Chip Bus with OCP Interface
Design of a Self-Motivated Arbitration Scheme for the Multilayer AHB Busmatrix.
Low Complexity and Fast Computation for Recursive MDCT and IMDCT Algorithms
An Efficient Architecture for 2-D Lifting-based Discrete Wavelet Transform
Power-Efficient Pipelined Reconfigurable Fixed-Width Baugh-Wooley Multipliers
A Spurious-Power Suppression Technique for Multimedia/DSP Applications
Design of AES (Advanced Encryption Standard) Encryption and Decryption Algorithm with 128-bits Key Length
DDR3 based lookup circuit for high-performance network processing
Multiplication Acceleration Through Twin Precision
32-bit RISC CPU Based on MIPS
High Speed Hardware Implementation of 1D DCT/IDCT
Efficient FPGA implementation of convolution
High Speed VLSI Architecture for General Linear Feedback Shift Register (LFSR) Structures
Implementation of a visible Watermarking in a secure still digital Camera using VLSI design
Implementation of FFT/IFFT Blocks for OFDM
Design and Implementation of Efficient Systolic Array Architecture for DWT (Discrete Wavelet Transform)

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